`timescale 1ns / 1ps

module axi_instr_counter #(parameter COUNTER_WIDTH = 5)
(
    input  wire   clk,
    input  wire   rstn,
    input  wire   add,
    input  wire   sub,
    output reg [COUNTER_WIDTH:0] cnt
);

always @(posedge clk or negedge rstn)
begin
    if(rstn == 1'b0)
        cnt <= 1'b0;
    else if(add == 1'b1 && sub == 1'b0 && (cnt <= ($unsigned(1<<COUNTER_WIDTH)-1) ) )
        cnt <= cnt + 1'b1;
    else if(add == 1'b0 && sub == 1'b1 && cnt >= 'd1)
        cnt <= cnt - 1'b1;
    //else if(add == 1'b1 && sub == 1'b1)
    //    cnt <= cnt;
    else
        cnt <= cnt;
end

endmodule
